MT2814

Programmable Baseband SoC

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Overview

Metanoia’s MT2814 is a higher end version of the MT2812. MT2814 is based on an integrated programmable baseband processor architecture for 5G applications such as standalone Small Cells as well as Split ones with Radio Unit (RU), Distributed Unit (DU), satellite and proprietary wireless connectivity applications. This innovative, highly integrated, programmable design is ideal for new and evolving standards or for custom wireless use cases such as Military, Aerospace, fixed wireless access or proprietary mesh schemes.

The MT2814 may be used as a high-performance co-processor for Open Radio Access Network (O-RAN) architectures where the vector engine complex can serve as a dedicated layer 1 accelerator. Metanoia 5G target markets for MT2814 include O-RAN products (DU and RU) and customer premises equipment (CPE) applications.

The MT2814 programming is supported by Codewarrior® tools and Metanoia reference application software and libraries.

Applications

The MT2814 SoC supports a scalable architecture which can help in building higher density applications by using multiple instances of the chip.

Target Market Segments

Sub-6GHz low density O-RAN RU market
Small Cell CPE (1T1R up to 8T8R) – standalone design that can directly connect to a 5G core network
High density RU
Complete end-to-end solution for RU including power amplifier (PA), transceiver, Digital Front-End (DFE), Low-PHY and fronthaul interface as specified by O-RAN

Use Cases

>> CPE/Small Cell Application System
4×4 MIMO for TDD with two Transceivers
4×4 MIMO for TDD 5G NR system One baseband chip MT2814 is connected to two 5G-NR Transceivers Larger MIMO configurations deployment possible by synchronizing multiple groupings
>> CPE/Small Cell Application System
2x2MIMO for FDD with two Transceivers
2×2 MIMO for FDD 5G NR system One baseband chip MT2814 is connected to two 5G-NR transceivers One 5G-NR transceiver is used for transmission, and one for reception

Specifications

Four CPU Complex	e200z7 Core running up-to 640 MHz 32-bit PowerPC Book E compliant 64 kB Local Data Memory 16 kB Instruction Cache 16 kB Data Cache Memory Protection Unit (MPU) with 24-entry descriptor table Embedded Floating-point APU (EFPU2) supporting scalar and SIMD single-precision floating-point operations Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations, using the 64-bit General Purpose Register file Performance Monitor APU supporting execution profiling
MPIC	Multi-processor interrupts management Support for up to 128 internal and 12 external interrupts
2 MB On-Chip Memory (OCRAM)
Standard 5-pin JTAG
I/O	Six I2C Multi-Master modes supported Six SPI interfaces with 4 Chip Selects FlexSPI supporting x4 serial NOR flash with one Chip Select Four GPIO Two DUART interfaces for debug console interface USIM interface for SIM card support Two lightweight LVDS communication protocol (LLCP)
One eight lane SerDes
Two Timebase (TBGen) one for each modem supported on MT2814
Two PCIe Gen3 interfaces	PCIe1 supporting x8/x4/x2/x1 lane operation in Endpoint (EP) mode only PCIe2 supporting x4/x2/x1 lane operation in both Root Complex (RC) and Endpoint (EP) mode
High Speed Data Conversion Subsystem(HS DCS)	Quad ADCs supporting receive channels: RXI1, RXQ1, RXI2, RXQ2 Quad DACs supporting transmit channels: TXI1, TXQ1, TXI2, TXQ2
Low Speed Data Conversion Subsystem (LS DCS)	Eight ADCs supporting receive channels: RXI1-RXI8, RXQ1-RXQ8 Eight DACs supporting transmit channels: TXI1-TXI8, TXQ1-TXQ8
Eight VSPA3 16SP Complexes	VSPA3-16SP running up-to 640 MHz (VSPA3 ISA, 16 Arithmetic Units Single Precision) Special Arithmetic Unit (SAU) 128 kB VCPU Program Memory 16 kB IPPU Program Memory 128 kB VCPU Data Memory 192 kB IPPU Data Memory DMA Aux DMA 64-bit master counter timing generation with timing advance and delay compensation
621 FC-PBGA package, 21 mm x 21mm

MT2814

Programmable Baseband SoC

Overview

Applications

Specifications

Reference Design